Counterfeit Mitigation Plan
Microchip USA understands the growing concern behind increasing volume of counterfeit parts entering the supply chain. We are continuously enhancing our quality management system and procedures to combat this problem and mitigate the risk of buying, receiving, and selling fraudulent/counterfeit electronic parts.
We maintain a register of Approved Suppliers. Criteria for selection, evaluation and re-evaluation are established. When a new source is used, Microchip USA has an approval process that ensures compliance with our Supplier Handbook, Quality Standards, and the terms and conditions of our Purchase Order. Microchip USA requires all Suppliers to acknowledge and confirm the understanding of requirements, customer flow down requirements, applicable statutory and regulatory requirements, and purchase order terms upon acceptance of a purchase order.
At Microchip USA, we are committed to providing the highest quality products and customer service that consistently meets customer requirements. We strive to continually improve our products and services by regularly measuring, monitoring, and reporting our performance against established quality objectives.
Third-Party Testing Capabilities
Inspecting electronic components under a microscope to determine if a device has been altered from its original state. During this process a device may show signs of non conformance or inconsistencies that help determine if a device has been used or if a device is new and original.
In the event of components whose origin is doubtful, an x-ray analysis can show if a chip is generally integrated in the component; it is used to examine if there is no deviation in the bond sequence or if improper bond wire junctions can be detected.
This is most commonly a wet chemical process. When a component is decapped, in this fashion, abrasive acids are used to corrode the surface of a component until the internal die wafer and wafer bonds are revealed. The internals are then examined for non-conformances.
Provides a means determining the solderability of device package terminations that are intended to be joined to another surface using SnPb or Pb-free solder.
The analysis of a small block of semiconducting material on which a given functional circuit is fabricated. The component’s die is compared with other components of its kind to determine if there are any non-conformances.
Most cost effective way to determine the probability a device is functional - compares a pin's signature measurements to every other pin looking for consistent I/V characteristics. This test detects gross defects such as opens, shorts, excessive leakage, ESD damage, etc. caused by improper handling or storage.
Sample(s) from each lot/date code are tested for evidence of remarking or resurfacing. Industry standard resistance to solvents test methods (SAE AS6081/AS6171, MIL-STD-202, Method 215, and JESD22-B107D) are performed to reveal any forged markings, coatings applied to disguise sanding marks, and other indications that the original device marking has been removed or covered. Testing includes 3:1 Marking Permanency Test, Acetone, 1-Methly 2-Pyrrolidinone and Dynasolve 750 tests.